To produce a MOSFET as one type of the MOS type semiconductor device, a plurality of p base regions are formed by diffusing impurities into selected areas of a surface layer of an n type semiconductor substrate such that pn junctions appear on the surface of the substrate, and n source regions are formed in surface layers of the p base regions in a similar manner. A gate electrode layer is then formed on an insulating film, over surfaces of channel regions provided by surface layers of the p base regions that are interposed between the n source regions and the n type semiconductor substrate, and a source electrode is formed in contact with both of the p base regions and the n source regions. A drain electrode is formed on the other surface of the n type semiconductor substrate. By applying a suitable voltage to the gate electrode, an inversion layer appears in each channel region, to reduce resistance between the drain electrode and the source electrode, and current is allowed to flow between the drain electrode and the source electrode through the inversion layer.
To produce IGBT as another type of the MOS type semiconductor device, an additional p type region is formed on the side of the drain electrode of the MOSFET. With the p type region thus added, the IGBT is capable of modulating the conductivity by utilizing injection of minority carriers.
The MOS type semiconductor devices as described above are widely used in switching circuits because the device provides low ON-state resistance and high switching speed, and can be easily controlled by changing voltage applied thereto.
In recent years, the MOS type semiconductor device used as a switching element in a switching circuit is more likely to receive surge voltage generated in the circuit, because of simplification of the switching circuit from which snubbers are eliminated, and reduction in the size of the semiconductor device. When the MOS type semiconductor device is used for cutting off current from an inductive load, for example, the voltage applied to the MOS type semiconductor device is increased due to energy stored in the inductor, and sometimes becomes even higher than power supply voltage. The resulting overvoltage stress may cause breakdown of the MOS type semiconductor device, and it has been thus desired to increase the breakdown voltage (avalanche withstand voltage) of the semiconductor device.
As one method for improving the capability of the MOS type semiconductor device to withstand avalanche breakdown, a part of the p base region is formed with a larger diffusion depth. The increase in the diffusion depth, however, affects the ON-state resistance and other characteristics of the device. For example, if the depth of a part of the p base region is changed from 5 .mu.m to 7 .mu.m in a certain MOSFET, the avalanche voltage increases by 25%, but at the same time the ON-state resistance increases by 15%. Thus, this method is not necessarily desirable in all aspects.
FIG. 6 shows an equivalent circuit of the MOSFET designed for improving the capability to withstand avalanche breakdown by another method.
In the circuit of FIG. 6, a series Zener diode array 3 is provided between the drain D and the gate G of the MOSFET. The series Zener diode array 3 includes a large number of pairs of Zener diodes that are connected in series such that each pair of diodes are formed back-to-back. In this arrangement, when the voltage applied to the drain D becomes higher than the clamp voltage of the series Zener diode array 3, a difference between the high voltage and the clamp voltage is applied to the gate G of the MOSFET, thereby to turn on the MOSFET. Namely, when an excess voltage is applied between the drain D and the gate G, the series Zener diode 3 functions to bypass the excess voltage between the drain D and the gate G so as to protect the device. Between the source S and the gate G, a pair of Zener diodes that are formed back-to-back and a resistor 6 are connected in parallel with each other. When an excessively high voltage is applied between the gate G and the source S, the pair of Zener diodes 5 function to bypass the excess voltage and protect the device. The resistor 6 functions to prevent high-voltage noise and others from being applied to the gate G due to disconnection of a gate lead, for example.
FIG. 7 is a cross-sectional view of MOSFET (as disclosed in U.S. Pat. No. 5,365,099) that realizes the circuit of FIG. 6.
The left-side part of FIG. 7 shows a generally used MOSFET, wherein an n drift layer 13 is laminated on an n+drain layer 11, and a plurality of p base regions 14 and p.sup.+ wells 15 inside these regions 14 are formed in a surface layer of the n drift layer 13. Further, n source regions 16 are formed in surface layers of the p base regions 14. A gate electrode layer 18 made of, for example, polycrystalline silicon is formed on a gate oxide film 17 over portions of the p base regions 14 that are interposed between the n source regions 15 and an exposed surface of the n drift layer 13. A source electrode 19 made of Al alloy is formed in contact with both the p base regions 14 and the n source regions 16. The source electrode 19 extends over the gate electrode layer 18 such that these electrodes 18, 19 are insulated from each other by an interlayer insulating film 21 made of boron phosphorous silica glass (BPSG). A drain electrode 10 made of Ti/Ni/Au is formed on the rear surface of the n.sup.+ drain layer 11. A unit structure having the n source region 16, source electrode 19, and other elements, above and below the p base region 14 will be called a cell structure. The cell structure is often formed in polygonal or rectangular shape, and a multiplicity of such cell structures are arranged in parallel with each other in an actual MOSFET.
An arrangement for improving the capability to withstand avalanche breakdown is illustrated in the right-side part of FIG. 11. An n.sup.+ contact region 26 is formed in a surface layer of the n drift layer 13, and an auxiliary electrode 22 is formed in contact with the n.sup.+ contact region 26. An array of a plurality of pairs of Zener diodes 23 that are connected in series is provided on a field oxide film 27 on the surface of the n drift layer 13. Each pair of the Zener diodes are formed back-to-back or oriented in opposite directions. The above-indicated auxiliary electrode 22 is connected to one end of the series Zener diode array 10, and an electrode 29 extending from the other end of the Zener diode array 10 is connected to the gate electrode 18 of the MOSFET.
In this structure, the potential of the auxiliary electrode 22 is almost equal to that of the drain electrode 10. When the voltage applied to the drain electrode 10 becomes higher than the clamp voltage of the series Zener diode array 23, therefore, a difference between the applied voltage and the clamp voltage is applied to the gate electrode layer 18 of the MOSFET, so as to turn on the MOSFET and protect the device.
The inventors of the present invention produced an IGBT provided with the arrangement for improving the capability to withstand avalanche breakdown, which has a similar structure to that of FIG. 7. FIG. 8(a) is a plan view of the IGBT chip thus produced. FIG. 8(a) shows a source electrode 1 of IGBT, a gate electrode 4, an auxiliary electrode 2, and a series Zener diode array 4 for improving the capability to withstand breakdown.
When the semiconductor device produced as described above was tested in the dynamic mode, so as to observe various dynamic characteristics thereof, the device broke down at a voltage lower than its static breakdown voltage, when the voltage applied to the device changes at a high rate (high dv/dt). The breakdown occurred at point A as indicated in FIG. 8(a), namely, at a point in a field insulating film formed between the series Zener diode array 3 and the n drift layer 13.
The semiconductor device also broke down at a relatively low voltage when cutting off current flowing from an inductive load. The breakdown occurred at point B as indicated in FIG. 8(a), namely, at an end portion of the source electrode close to the series Zener diode array 3.